Design and implementation of a near maximum likelihood decoder for Cortex codes

International audienceThe Cortex codes form an emerging family among the rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient Maximum Likelihood (ML) decoder for Cortex codes. It first reviews a dedicated architecture that takes advantage of the particular structure of this code to simplify the decoding. Then, we propose a technique to improve the architecture by the generation of an optimal list of binary vectors. An optimal stopping criterion is also proposed. Simulation results show that the proposed architecture achieves an excellent performance/complexity trade-off for short Cortex codes. The proposed decoder architecture has been implemented on an FPGA device for the (24,12,8) Cortex code. This implementation supports an information throughput of 225 Mb/s. At a signal-tonoise ratio Eb/No=8 dB, the Bit Error Rate equals 2 × 10^−10, which is close to the performance of the Maximum Likelihood decoder

Reconfigurations algorithmiques et architecturales régulées (contribution à l'auto-adaptation des systèmes embarqués)

Reconfigurable systems are, today, a solution to efficiently respond to the economic constraints that request more flexibility and hardware component reuses and to the performance constraints requested by increasingly complex application. Reconfiguration management is not completly controlled and little research works aim the decision and the self-adaptation of embedded systems according to their environment. Thus, we suggest, in this thesis, a solution for designing self reconfigurable embedded systems according to quality of service, performance and power consumption objectives. Our approach is based on two originale contributions. The first one is a decision component based on an adaptive close-loop model updated with real measures, moreove it provides a clear separation between application specific and global decisions. The second one is an extension of operation system services for the transparent management of hardware and software tasks according to configuration decisions. The self adaptive method has been theoretically formalized and implemented on a real-life demonstrator that have been able to demonstrate its relevance on a complexe image processing application. The choice has been made to design a smart camera for objects tracking. Power consumptions, logic area and execution time measures bring the proof of weak perturbations from self-adaptive components on system performances.Les systèmes reconfigurables sont, aujourd'hui, une solution pour répondre efficacement aux contraintes économique qui fait tendre vers plus de flexibilité et l'intégration de composants matériels sous la forme d'IP et aux contraintes de performances exigées par des applications de plus en plus complexes. La gestion des reconfigurations n'est toutefois pas encore totalement maîtrisée et peu de travaux de recherche ne s'intéressent à la prise de décision et à l'auto-adaptation du système vis-à-vis de son environnement. Le cadre de la thèse correspond à ce besoin clé. Ainsi, nous proposons, dans cette thèse, une solution pour concevoir un système embarqué auto-configurable répondant à des objectifs de qualité de service, de performance et de consommation énergétique. Notre approche repose sur deux contributions originales. La première est un composant de décision reposant sur un modèle à rétroaction adaptatif mis à jour par des mesures réelles et qui fournit en plus une séparation claire entre les décisions spécifiques à l'application et celles globales. La deuxième est une extension des services d'un système d'exploitation pour la gestion transparente des tâches matérielles et logicielles selon les configurations décidées. Enfin, nous avons mis en oeuvre un démonstrateur réel. Le choix a été fait de réaliser une caméra intelligente effectuant un suivi d'objet. Des mesures de consommations, de surfaces et de temps d'exécution apportent la preuve du faible impact des éléments de l'auto-adaptation sur les performances du système.LORIENT-BU (561212106) / SudocSudocFranceF

Specification and os-based implementation of self-adaptive, hardware software embedded systems

International audienc

Reconfiguration Management in the context of RTOS-based HW/SW embedded systems

International audienceThis paper presents a safe and efficient solution to manage asynchronous configurations of dynamically reconfigurable system on chip. We first define our unified RTOS-based framework for HW/SW task communication and configuration management. Then three issues are discussed and solutions given: the formalization of configuration space modeling including its different dimensions, the synchronization of configuration that mainly addresses the question of task configuration ordering and the configuration coherency that solves the way a task accepts a new configuration. Finally we present the global method and give some implementation figures from a smart camera case study

RTOS-based hardware software communications and configuration management in the context of a smart camera

This paper deals with the question of task communication and configuration dynamic management in the context of hardware and software implementations. Our approach is based on a couple of local and global reconfiguration managers that enable firstly to monitor the embedded system and secondly to separate application specific and system level configuration decisions. Then we detail the abstraction layer we introduce to handle inter-task communication and synchronization independently from their implementations. Finally we present how our solution is implemented in the context of a smart camera. Key Words: RTOS for HW/SW reconfigurable systems, configuration management, monitoring

μSPIDER CAD TOOL: CASE STUDY OF NOC IP GENERATION FOR FPGA

International audienceThis paper introduces the μSpider CAD tool for NoC design under latency and bandwidth constraints and describes the different steps of the associated design flow. We show how the tool can be used to automatically generate a NOC IP compliant with Xilinx EDK tool. We present synthesis results and a real implementation of a video application based on a multi-processor architecture. Finally we conclude about research to be done at application/OS levels above current work to achieve a complete and efficient implementation of a multi-processor embedded system

Système de surveillance

Le système de surveillance défini dans ce brevet permet la surveillance d'équipier sur un bateau quelque soit son type ( plaisance, marchande, pêche). Le système est basé sur des technologies radio (rubee, RFID) et permet la surveillance temps réel d'un équipage. De plus le système déposé possède un encombrement et un coût faible tout en ayant une facilité de mise en oeuvre importante